//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Mon Nov 11 16:56:13 2019
//Host        : DESKTOP-EVCEGS1 running 64-bit major release  (build 9200)
//Command     : generate_target Add_1bit.bd
//Design      : Add_1bit
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "Add_1bit,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Add_1bit,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=5,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "Add_1bit.hwdef" *) 
module Add_1bit
   (A,
    B,
    CI,
    CO,
    Y);
  input A;
  input B;
  input CI;
  output CO;
  output Y;

  wire A_1;
  wire B_1;
  wire CI_1;
  wire xup_and2_0_y;
  wire xup_and2_1_y;
  wire xup_or2_0_y;
  wire xup_xor2_1_y;
  wire xup_xor2_2_y;

  assign A_1 = A;
  assign B_1 = B;
  assign CI_1 = CI;
  assign CO = xup_or2_0_y;
  assign Y = xup_xor2_2_y;
  Add_1bit_xup_and2_0_3 xup_and2_0
       (.a(A_1),
        .b(B_1),
        .y(xup_and2_0_y));
  Add_1bit_xup_and2_1_2 xup_and2_1
       (.a(CI_1),
        .b(xup_xor2_1_y),
        .y(xup_and2_1_y));
  Add_1bit_xup_or2_0_3 xup_or2_0
       (.a(xup_and2_1_y),
        .b(xup_and2_0_y),
        .y(xup_or2_0_y));
  Add_1bit_xup_xor2_1_2 xup_xor2_1
       (.a(A_1),
        .b(B_1),
        .y(xup_xor2_1_y));
  Add_1bit_xup_xor2_0_4 xup_xor2_2
       (.a(xup_xor2_1_y),
        .b(CI_1),
        .y(xup_xor2_2_y));
endmodule
